Chris Gammell is an electronics devotee, electronics designer for Analog Life, LLC, co-host at The Amp Hour Podcast, and founder & instructor at Contextual Electronics.
We were four minutes into an episode when we realized we weren’t recording. So this show is just a tribute. Chris just launched the Contextual Electronics Podcast! There are already three episodes released, and another three recorded! Sophy Wong Stephen Hawes Erik Larson Chris uses Streamyard for recording video. We use Zencastr for The Amp Hour. Cameras continue to improve…but don’t have much effect on Dave and Chris Eurocircuits has a great DfM tool because there’s no human in the loop for checking your files We wish that was the case for sales engineers as well…it’s better when you don’t need to talk to humans! Chris has been dealing with gerber problems. Dave ended up making a video about this after this episode was recorded. Gerber “aperture” is like an etch-a-sketch where light goes through a certain diameter hole to expose the pattern. Dave has a new video about someone who created a similar design at the same time. We have discussed this once or twice before on the show. “Technology transfer” when an employee goes from one company to another and a design concept follows them. Intel sending work to TSMC. They also got rid of their lead engineer. ARM is up for sale again. Apple suppliers are talking about purchasing, as are Nvidia. Softbank has had some real duds lately, notably WeWork. Arrow isn’t buying IEEE GlobalSpec. They do own EETimes though. Google is offering training courses that may lead to hiring for them. It will be as low as $300 and administered through Coursera. Scott Galloway talks about how education and training will change on the Prof G show. Brad Feld was on the Tim Ferriss podcast. Shahriar did a great troubleshooting video last week, showing how to diagnose different RF sections. The Ultimate Electronics online textbook has links out to 100+ simulations to showcase concepts. Chris has been reading some new books lately: The Baroque Cycle (fiction), a trilogy by Neal Stephenson Hands-On RTOS with Microcontrollers Ultralearning Range Dave has never watched…The Office??
Welcome Mohammed Kassem, CTO of eFabless! This is well timed after we talked with Tim Ansell in episode 501 on about Google’s announcement around the open source PDK. OpenLANE was mentioned in that episode, but that is run by eFabless Traditionally, the semi industry had been very closed. Small companies struggled to get a custom chip made, and it was still $500K to $1M to start. When efabless started, they wanted to design in the browser Was the open PDK the gating moment? The PDK is the IP of the fab. eFabless uses the 130 nm PDK from Global Foundries, 80 nm from Sky Fab (which are not open). Does it have to be on the browser? No, but that made it easier to deal with closed source IP. Lots of people are working on it around the world, even at highGer latencies Black box design / only knowing the input and output eFabless offers both open and closed IP Mohammed worked in smartphone chip development, starting in 2000. He designed chips for smartphones at TI. He saw that there can be as few as two people designing chips at a company, but the rest of the company is designing infrastructure that makes it possible. What if this infrastructure was outside of any one company? He asked if it can look like an app store, since there would be small players who could access the resources and develop small ideas. Was this a validated idea? Do engineers want this sort of thing? Looked at Topcoder as an example from the software world. There were also data points from the open source world. What is the volume for making a custom chip? The first chip off the line costs the entire NRE. Each additional chip amortizes that up front cost. Need to sell enough to cover the NRE cost with the margin in the chip. eFabless want to reduce the volume requirement so it’s less of a hassle when someone is asking “Do I need an ASIC?” That knowledge is residing on the IC side, so a system dev wouldn’t consider doing it Reasons for using an ASIC (after getting the costs down) Size Configurability Security Supply chain reliability Obsolescence mitigation Using the IP to pitch a startup idea to investors Raven microcontroller uses the RISC V core by Claire Wolf. Raven isn’t all open source (all the way down to the transistors), but a lot of it is. Can clone an ARM chip on the platform, without needing to do much design. Anything with closed IP has to stay online. With the openPDK, there is striVe SOC family. It has no analog on it at all. Adding memory is like an FPGA using block ram Mohammed will be doing a FOSSI dialup talk on Aug 25th OpenROAD vs OpenLANE OpenROAD can do 1M+ gates, previously was only 100K GDS is “graphic design system”. It is like gerbers all in one file, but also has thickness information. Xfab – 350 nm for high voltage, 180 nm for normal Global Foundries 130G, can do front end with it What does it take to get a new fab onto their platform? GDS is readable in any tool, but it’s not as easy as it might be with large scale EDA Start with design rules, which are in a PDF manual Validating the designs and design rules is done against known designs. The number of layouts will go up a lot with the open source PDK, which is why getting more designs is important! This will allow people to push the rules Analog process always trails digital Hopefully this is all the beginning, with Skywater as a beachhead for convincing other fabs to open up. Statistically speaking, more designs means more potential hits in the marketplace (for Skywater) It’s like a currency: convert IP to a process technology is valuable, but doesn’t translate well to other places. Parallel processing might be possible now that there are more people testing Join the slack channel The process requires a lot of knowledge, but wants to simplify the knowledge level Try out your very own Raven configuration! Chris was able to do it with a few clicks during the recording. The goal with OpenLANE is to get to no design rule errors NEC wanted to work with Raven on parts and ended up customizing past the configuration tool online. Learn more at Join the Slack Channel to talk with others and get involved! or
Dave had a recent video about selecting different op amps for the microcurrent (maintaining engineering!) ADI buying Maxim Maxim sampling policy Will there be a large amount of crossover parts? Microchip sent out a letter asking for better visibility into the backlog Boards with stackup Video about reviewing PCBs of forum member Chris borrowed an idea from past guest Luke Valenty about how to use pill shaped pads on the tinyfpga bx. This enables using a larger Process for PCBs “Lowest common denominator design” is the idea of choosing a PCB fab that has a very small space/trace, but only needing it for the smallest chip. CSP – Chip Scale Package “Putting the EV in EEVblog” (looking at electric vehicles) Dave bought a teardown report of the BMW i3 on and it’s awesome. Forensic teardowns Intel video inside the chip fab We were sad to hear that Grant Imahara passed away last week. Watch his former co-host Adam Savage talk about memories of Grant. Image from this video about fractions
Welcome back, Tim ‘Mithro’ Ansell! Tim has been on the show twice before: First time was talking about microcontroller and making a device out of that Second time was talking about FPGAs Third time is looking at creating the ASIC Tim says the next level down will be making the actual chips like Sam Zeloof, but he prefers bits to atoms. Talk at Chaos with Bunnie about dabbling in the others’ fields, like thinking about the lifetime of software (and applying quality engineering) What is an open source PDK? Github repo Three main components to building an IC The RTL and design (code) The tools – compiler / interpreter in SW How does the physics work? Called the PDK – process design kit In machine readable form Similar to the stackup of a PCB Tim likes the tool SKiDL by past guest Dave Vandenbout. Mike Englehardt has been on before talking about SPICE. Why were PDKs secret before? Especially since it would be very hard to reverse engineer the PDK In the 80s it was open, but it changed over time. Chris posits because of VC investment? Now it’s cultural that the chip industry is not open “Open source has won in the sofware world” and the arguments feel the same QuickLogic officially supporting their tools with open source tools, as stated in a blog post by CEO Brian Faith We are still taking entries to win a board from episode 500 RISC V ISA (instruction set architecture) “The secret power of open source means engineers don’t have to spend time talking to lawyers” Open source standardizes legal equations The ASIC world has many groups of lawyers Only ideas that people are extremely confident about will get explored Moore’s law slowing down, compute needs growing Taking risks is hard because of all the roadblocks RISC V has opened up the ISA space to try exploring ideas that others had written off as bad ideas Tim gave a FOSSi “Dial Up” talk, which we will refer to at different timestamps to discuss the slides he reviews. Single core has flattened out for 10 years (7 minute mark on the video) More cores needs more memory bandwidth Power consumption issues Tim is in a group the focuses on developer productivity at Google That’s why they’re contributing to tools to make things faster Security is also dependent upon how fast you can deploy changes Making hardware accelerators using TPUs Using machine learning to develop TPU 130 nm came out in 99 (26 minute mark) The PDK and resulting silicon will be used for areas where cost > performance, like IoT. Good for microcontroller, but not a high speed Beagleboard has PRUs They expect some users will make specialized devices, like putting a RISC V per pin or similar. What’s the plan for analog? First thing released was digital standard cells, but they plan to publish low level transistor models, including parametric models. Unfortunately they are currently blocked on getting that work released. What tools are available? Similar to FPGA toolchain sides First step for FPGA and ASIC is synthesis, like using Yosys (lead by Claire Wolf) P&R is different More freedom in ASICs QFlow ASIC PNR (Tim Edwards) FPGA PNR are different toolchains: NextPNR (lead by Dave Shah) VPR (grandfather of Quartus 2) DARPA launched a program called IDEA (Andreas Olofsson), which resulted in another PNR for ASICs: The Open Road project Tools for doing an open source flow Submitted list by sine_osc Magic (older than the BSD license!) KLayout SPICE Xyce is fast LTSpice used by LT designers Schematic capture is still not easy (maybe KiCad?) Google will be doing a free shuttle run for open source chips Will be sending it to eFabless, they will bundle the shuttle 40 designs total (unless they get a large response) Wafer chip scale package (CSP) 4x4mm 50 i/o, 40 will be for design Might send back chips on castellated PCB To get your design approved, it must be using the right license. They will release a full list of licenses that will work, but Apache2 is guaranteed. Also needs to pass DRC, which will be published in the repo soon. Skywater PDK slack channel Lottery system if they get more than 40 designs Will be starting first run in Mid-November, Will be doing more runs after that. Out of 16 mm^2, only 10 mm^2 is available. The rest will be for “the harness”, a RISC V processor that can connect ‘virtual GPIO’ to turn things on or off. As a reference for size, could probably fit 10 RISC V cores on the 10 mm^2 In contrast to MOSIS or Europractice, they want to fab out 100 – 400 of the chips so that they can share. Slack channel skywater-pdk J-Core, an SH based processor Power PC is now an open ISA Tim has published an Inspiration document. If you’re interested, you should join the mailing lists, especially the announce one. The slack invite link is on the announce list. They will try to set up an invite bot for later. Check out the FOSSi dial up talk series for future information about development. Mohammed from eFabless will be giving a talk about Open Road and will be showcasing demo chips, which are currently out for manufacturing. These might act as good templates. Need tutorials on all of the software (KLayout, MAGIC) Project from University of Michigan, FASoC, treats analog design like digital design. “Screaming inside their heart” Craig Bishop episode Adrian Tang episode The physics act more ideally in the small space of silicon Hoping to have a similar OSHpark for silicon “Chips4makers” is one that is trying to make “the OSH Park for ASICs”, but they are more focused on retrocomputing. Trying to seed and build an ecosystem “The things that will be most successful in this space will be those that build on each other and work together” Traditional ASIC designers should be prepared to do thing differntly Can open source be profitable? IBM bought Red Hat for $30B The next wave of software is “software AND”, the hardware is just a means to an end Contact Tim directly: Better to go on the slack and ask there
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Chicago, Illinois, USA
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1 week, 3 days
Podchaser Creator ID logo 836904